1. Technical Field
Embodiments of this disclosure relate generally to a non-volatile memory device and a method of manufacturing the same and, more particularly, to a non-volatile memory device having a three-dimensional (3-D) structure and a method of manufacturing the same.
2. Related Art
As the memory device field, such as non-volatile memory devices, is advanced, there is an increasing demand for the high degree of integration of the memory devices. In a known art, the degree of integration of memory devices within a certain area is increased by using a method of reducing the size of memory cells which are arranged over a semiconductor substrate in a two-dimensional (2-D) manner. A reduction in the size of the memory cells, however, is physically limited. For this reason, there is recently proposed a method of high integrating memory devices by arranging memory cells over a semiconductor substrate in a 3-D manner. If, as described above, the memory cells are arranged in a 3-D manner, the area of the semiconductor substrate can be efficiently utilized and the degree of integration can be improved as compared with the memory cells arranged in a 2-D manner.
From among 3-D non-volatile memory devices, a 3-D non-volatile memory device having U-shaped memory strings includes U-shaped channel layers. Each of the U-shaped channel layers includes first and second vertical channel layers and a pipe channel layer for coupling the first and the second vertical channel layers. The 3-D non-volatile memory device further includes a plurality of cell gates formed along each of the first and the second vertical channel layers and stacked and isolated from each other with an interlayer insulating layer interposed therebetween and select gates formed on both ends of the U-shaped channel layer. The cell gates and the select gates are formed to surround the U-shaped channel layer. A memory layer is formed between the cell gates and the U-shaped channel layer. The memory layer includes a tunnel insulating layer formed to adjoin the outer wall of the U-shaped channel layer and surround the U-shaped channel layer, a charge trap layer formed to surround the tunnel insulating layer, and a blocking insulating layer formed to surround the charge trap layer. A gate insulating layer is further formed between the cell gates and the U-shaped channel layer.
The 3-D non-volatile memory device can store data by injecting electrons into the charge trap layer formed at the crossing of the cell gates and the U-shaped channel layer and can erase data by discharging electric charges, injected into the charge trap layer, from the charge trap layer toward the U-shaped channel layer. In particular, in order to generate holes on the select gate side in an erase operation, Gate Induced Drain Leakage (GIDL) is induced, and the generated holes are introduced into the U-shaped channel layer. Accordingly, a potential difference is generated between the U-shaped channel layer and the charge trap layer, so that the electrons within the charge trap layer are discharged. In this erase operation, however, there are disadvantages in that erase operation signals have complicated waveforms and the erase time is increased in order to induce the GIDL and the reliability of the select gate is deteriorated.